The present invention generally relates to information processing apparatuses, and more particularly to an information processing apparatus for processing digital data at a high data processing speed and suited for application on a general purpose microprocessor.
In the recent general purpose microprocessor, the operation frequency is high and a processing such as the pipeline processing is carried out to satisfy the demands for high-speed data processing.
According to the pipeline processing, before one operation ends a next operation is started when repeating similar processes. Hence, a plurality of operations are executed in an overlapping manner so as to realize a high-speed processing by hardware. For example, the pipeline processing of the microprocessor is made up of five stages which are an instruction decode stage, an effective address calculation stage, an operand read stage, an operand process execution stage and an operand write stage. In this case, the read out from the register and the decoding of the instruction must be carried out in the instruction decode stage in order to enter the effective address calculation stage. Hence, in order to realize the high-speed data processing, the instruction decode stage must be carried out at a high speed, that is, the read out from the register and the decoding of the instruction must be carried out at a high speed.
FIG. 1 shows an example of a conventional information processing apparatus. An information processing apparatus 50 shown in FIG. 1 includes an instruction register 51 for storing an instruction, a bus 58 for transferring the instruction, an instruction decoder 52 for decoding the transferred instruction, a register specifier part 53 for specifying a register depending on a decoded result from the instruction decoder 52, a general purpose register part 54 including a stack pointer and a plurality of general purpose registers, a special purpose register part 55 including a plurality of special purpose registers, an address calculation part 56 for calculating an effective address from the decoded result and a read out register content, and a memory 57 to which an access is made based on a calculation result.
When the instruction is stored in the instruction register 51, the information processing apparatus 50 transfers an instruction code within the instruction to the instruction decoder 52 via the bus 58. The instruction decoder 52 decodes the instruction code and supplies a decoded result to the register specifier part 53. The register specifier part 53 specifies a read operation from the general purpose register part 54 or the special purpose register part 55. Based on the register content read out from the general purpose register part 54 or the special purpose register part 55, the address calculation part 56 calculates the effective address and makes access to the memory 57 at this effective address. Thereafter, the information processing apparatus 50 carries out various processes based on the contents of the memory 57 and the like.
When the stack pointer is specified by the general purpose register part 54, the stack pointer may be read out as the stack pointer itself and the stack pointer may be read out as the general purpose register depending on the decoded result. For this reason, an access to the register can only be made after the decoding of the instruction. Therefore, there is a problem in that the speed of the decoding stage cannot be reduced considerably, and it is thus difficult to set the operation frequency high.